Field of the Invention
Advances in the design and fabrication of microprocessors in the past few years has resulted in a dramatic increase in processor speeds. In fact average speeds have increased more than four fold in the last decade alone. At the same time peripheral input/output busses have remained substantially constant. For example, the Industry Standard Architecture (ISA) bus operates at 8 MHz while many microprocessors operate in the 100-200 MHz range.
As the discrepancy in speed increases, it has become unfeasible to directly connect the I/O bus to the microprocessor. PC (Personal Computer) developers have solved this problem by providing "bridge modules" which disconnect the microprocessor/memory from the I/O bus. While this greatly improves the performance of the microprocessor when it is working from memory or cache, it typically does so at the expense of the microprocessor I/O bus interface. In today's PC environment it is typical for a microprocessor to wait 100 or more processor cycles for each I/O bus access.
Under these conditions the amount of time the microprocessor spends handling devices attached to the I/O bus can significantly impact the microprocessor's performance. Many high speed peripheral devices, such as disk drives and network controllers, are designed to be bus masters which allows these devices direct memory access (DMA). This moves the burden of data movement to the peripheral from the microprocessor resulting in an improvement in the utilization of the microprocessor bandwidth. However, microprocessor communication with peripheral devices still remains a major area for improvement.
Most peripheral component devices communicate with the microprocessor over a relatively slow (ISA), interrupt driven input/output bus. The device signals the microprocessor that it needs service by driving a bus interrupt signal active and waiting for the processor to provide service. A typical sequence includes the steps listed below:
1. the processor stores in memory all necessary information (data, status, etc.) relative to the current operation it is performing (typically a user application); PA0 2. the processor reads from memory all information necessary to service the interrupt; PA0 3. processor sequentially queries each device on the indicated interrupt to ascertain which needs service; PA0 4. The interrupt routine will require multiple I/O bus accesses to fully service the request; and PA0 5. after the interrupt request, the processor must reverse steps 1 and 2 in order to resume processing the interrupted operation.
The above sequence is generally referred to as context switching and can consume thousands of processor clock cycles for every generated interrupt. In those instances where there are many connected peripheral devices each generating many service interrupts, the processor has little time, if any, to service resident user applications.